The present invention relates to frequency detectors generally and, more particularly, to a frequency difference detector with a programmable number of channels.
Conventional frequency difference detectors have a fixed number of channels. For multi-channel applications, one or more channels can be powered down. If a particular channel is powered down, there is no need to evaluate the powered down channel. An example of a conventional multi-channel frequency difference detector may be found in co-pending U.S. application Ser. No. 09/047,595, now U.S. Pat. No. 5,952,888, which is incorporated by reference in its entirety.
Conventional frequency difference detectors typically rely on ripple counters, which are slow and not easily scaled to high speed operation (e.g., 1-3 Gigabits/s data rates). Conventional frequency difference detectors lack (i) an output for further synchronous processing and (ii) a test clock input. In addition, with a Block Based Design Methodology (BBDM) it is preferable that the same frequency difference detector (FDD) be implemented on multiple end products without modification. Such an implementation is inefficient with conventional approaches. Commercial products may have a different numbers of channels (e.g., one channel may be needed for a single channel device, and four channels may be needed for a quad channel device, etc.).
The present invention concerns an apparatus comprising a first circuit configured to present one or more control indication signals in response to (i) one or more select signals, (ii) one or more clock signals and (iii) one or more divider control signals. The first circuit may be configured to select an active channel from a plurality of channels in response to the one or more select signals.
The objects, features and advantages of the present invention include providing a frequency difference detector that may (i) have a user programmable channel count mechanism, (ii) have a timing pulse generation sub-block, (iii) be implemented with polynomial counters including trap and overrange circuitry optimized for polynomial counters, (iv) have an output OOLICLK, and/or (v) have a test clock input.